1. Field of the Invention
The invention relates in general to electronic circuit design and more particularly to scan chains in electronic circuit design.
2. Description of the Related Art
Modem integrated circuit (IC) design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the IC chip design process. Generally, an IC circuit design process begins with an engineer using a high level design language (HDL) such as Verilog or VHDL, to define the input/output signals, functionality and performance characteristics of the circuit. This information is provided to a computer that runs a logic synthesis program that generates or compiles a specification defining the integrated circuit in terms of a particular technology (e.g., very large scale integration). More specifically, the specification may include a netlist that specifies the interconnection of functional cells in the circuit. The specification serves as a template for the design of a physical embodiment of the circuit in terms of transistors, input pins, output pins, wiring and other features involved in the layout of the chip. The layout is a geometric or physical description of the IC that may consist of a set of geometric shapes in several layers.
An IC chip layout is designed by providing the specification to a computer that runs computer aided design programs that determine an optimal placement of functional cells and an efficient interconnection or routing scheme between cells to achieve the specified functionality. Placement is a process to assign location and orientation of a library cell or of IP (intellectual property) in a predefined area usually called a floorplan of an IC. Intellectual property, may be a licensed proprietary design component, for example. Placement result is a resulting specification of the position and orientation of cells or IP relative to each other in a floorplan of an IC design. Computer implemented placement algorithms assign locations to the functional cells so that they do not overlap, so that chip area usage is optimized and so that interconnect distances are minimized. Chip area optimization permits more functional cells to fit into a given chip area. Wire length minimization reduces capacitive delays associated with longer nets so as to speed up the operation of the chip. Routing typically follows placement in the layout design flow. Computer implemented routing algorithms determine the physical distribution of wire interconnects through the available space. For example a placement process may use various cost functions to achieve functional cell placement estimated to minimize wire length and estimated to minimize wire congestion during a subsequent routing process.
FIG. 1 is an illustrative example of a typical possible placement result 102 in the layout domain of an IC design. Sequential cells 104 and 106 are triggered by first clock CLK1. Sequential cells 108 and 110 are triggered by second clock CLK2. Functional unit 112 feeds data to sequential element 104. Sequential cell 106 feeds data to functional unit 114. Functional unit 116 feeds data to sequential cell 108. Sequential cell 110 feeds data to functional unit 118. The sequential cells are placed adjacent to the functional units they serve. Note that at this juncture of the design process, wire connections have not yet been made to interconnect these components. During a subsequent routing process, wires are routed to interconnect the sequential elements and functional units. The sequential cells shown in the drawing are D-flip-flops (dff's). However other types of sequential cells such as SR flip-flops or JK flip-flops sometimes are used instead. The functional units may comprise combinational logic. The first and second clocks may have the same frequency but different phase, for example.
As integrated circuits have become more complex and densely packed with gates, they have become progressively more difficult to test in order to ensure desired functionality. As a result, testability has become an increasingly more important and challenging goal of the integrated circuit design process. Computer programs that aid in the design of testability circuitry for integrated circuits are often referred to as design for test (DFT) processes. One approach to DFT, for example, is to take a netlist representing an integrated circuit design generated and to add and/or replace certain memory cells and associated circuitry of the netlist with special memory-cells, called scan cells, designed to allow application of test vectors to certain portions of an integrated circuit produced according to the design.
Scan cells are interconnected to form scan chains. During test mode operation, scan test vectors in the form of a series of logical 1 and logical 0 test vector values are loaded into the scan cells of a scan chain. The circuit is caused to operate for a prescribed number of clock cycles using the test vectors as input. The results of the circuit operation can be captured in the form of logical 1 and logical 0 scan test results values. Scan test vectors and scan test results shall be referred to collectively as scan data. The same scan chain scan cells used to read in the test vectors can be used to capture the test results. The captured values are read out of the scan chain for observation and analysis. The results can be compared with expected results to determine whether the circuit operates as expected and to thereby determine whether defects are present.
Mission mode circuitry comprises those portions of the IC used to perform the circuit's intended purpose, such as to serve as an adder or shift register or some application specific circuit. Test mode circuitry comprises those portions of an IC used to facilitate testability. Scan cells perform dual roles. During mission mode operation, the scan cells serve as memory components within the functional design. During test mode operation, scan cells serve to input test vectors and capture test results.
FIG. 2 is an illustrative drawing of one example of a scan cell 202 comprising a D-flip-flop (dff) 204 and a multiplexer 206. The multiplexer 206 receives as input a data value (D) and a scan-in value (SI). The multiplexer provides its output to a D input of the dff 204. A scan enables (SE) control input (SE) controls whether the multiplexer 206 provides the D value or the SI value to the D input of the multiplexer. In mission mode, the multiplexer 206 provides the D input to the D input of the dff. In test mode, the multiplexer 206 provides the SI input to the D input of the dff 204. A Q output of the dff 204 serves as a shared output node that provides mission mode data output during mission mode operation and that provides scan mode output (SO) data during test mode operation. The SO and Dout pins could become a shared pin for the scan cell 202, depending on various cell library technology. For simplicity of discussion, we treat SO and Dout pins as two different pins in the scan cell.
In some earlier electronic design automation systems, a placement process produced and initial placement of sequential cells and functional cells of an IC design before a scan cell insertion process replaced any sequential cells with scan cells. Following scan cell insertion, however, the initial placement often had to be adjusted since inserted scan cells generally occupy more area than the sequential cells they replace. Moreover, during scan cell insertion, delay elements such as buffers or lockup latches might be added to avoid hold time violations in a scan chain having scan cells triggered by different clock domains. Accordingly, the initial placement often required adjustment in order to fit in the delay elements.
For example, FIG. 3 illustrates an initial placement requiring adjustment of scan cell placement and showing addition of a lockup latch. More specifically, this drawing endeavors to illustrate problems of overlapping cells that can result from scan cell insertion. For instance, an initial placement such as that in FIG. 1 may be subjected to a scan cell insertion process resulting in a transitory placement 302 like that of FIG. 3. Basically, scan cell 304 replaces sequential cell 104. Scan cell 306 replaces sequential cell 106. Scan cell 308 replaces sequential cell 108. Scan cell 310 replaces sequential cell 110. Lockup latch 312 is added to avoid hold time violations when the four scan cells are stitched into a single scan chain for test mode operation, since scan cells 304 and 306 are triggered by the first clock CLK1, and scan cells 308 and 310 are triggered by the second clock CLK2. FIG. 3 shows that local overlap of scan cells and functional can occur as a result of scan cell insertion. Placement of overlapping cells violates design rules and is unacceptable. One prior technique for correcting for local overlap resulting from scan cells insertion was to initiate an engineering change order to make small scale localized changes in cell placement to remove overlaps and to squeeze in any new delay elements such as lockup latches.
In other prior electronic design automation systems, a netlist was first compiled from a behavioral specification. Scan chains then were inserted into the netlist. The netlist with inserted scan chains then was passed to a layout process where functional cells and dual-purpose scan cells were placed and routed. However, in the past, scan chain constraints have lead to wire congestion problems and to excessive wire length problems, for example.
FIG. 4 illustrates a wire congestion and wire length problems that can arise due to a scan chain placement result of 402 with scan cell order constraints. In the example of FIG. 4, it is assumed that there is a scan chain design constraint that requires that scan cell 404 is the first in the scan chain, followed in order by scan cell 406, scan cell 408 and scan cell 410. Lockup latch 412 is assumed to have been added to avoid hold time violations since a first clock CLK1 triggers scan cells 404 and 406, and a second clock CLK2 triggers scan cells 408 and 410. It is further assumed that a placement process placed a sequential cell (not shown) replaced by scan cell 406 in placement order before a sequential cell (not shown) replaced by scan cell 404. Since scan cell order is a constraint in this example, the order of scan cells in the scan chain was maintained despite the unfortunate placement result. Thus, the scan cells were stitched together in the constraint order. In this example, the placement result 402 leads to wire congestion around scan cell 406 due to wires 413, 415 and leads to a relatively long wire 417 between scan cell 404 and the lockup latch 412.
FIG. 5 illustrates an excessive wire length problem that can arise due to a scan chain placement result 502 with scan cell order constraints. More particularly, this drawing illustrates a placement 502 with a long wire 519 from scan cell 406 to lockup latch 412. In the example of FIG. 5, it is assumed that there is a pre-existing scan chain design constraint that requires that scan cell 404 is the first in the scan chain, followed in order by scan cell 406, scan cell 408 and scan cell 410. Lockup latch 412 is assumed to have been added to avoid hold time violations since a first clock CLK1 triggers scan cells 404 and 406, and a second clock CLK2 triggers scan cells 408 and 410. It will be noted that in this example, the placement process placed scan cells in a placement order consistent with the scan chain order constraint, Unfortunately, the placement of FIG. 5 results in what appears to be an excessively long wire 519 between scan cell 406 and lockup latch 412, although there seems to be no excessive wire congestion problem.
In some earlier layout systems, the layout of a design was not influenced by the test mode logic (i.e., scan cells). As a result, in many circumstances, the layout process would break up the scan chains inserted during a scan insertion process and place the scan cells in a way that the that the mission mode circuitry was not affected by the test mode circuitry. The layout process then would reconnect the scan chain based upon the placement of the scan cells. This process has been referred to as placement-based scan chain ordering.
A problem can arise with placement-based scan chain ordering in IC designs that have multiple clock domains or sequential cells that trigger on different clock edges, such as those of FIGS. 1, 3–5, for example. For instance, a constraint-driven scan insertion process may insert a scan chain in which the scan cells are ordered so that positive edge-triggered scan cells precede negative-edge triggered scan cells. In that case, simplistic placement-based scan chain ordering could mix scan cells with different clock edges resulting in faulty operation of the test mode circuitry.
U.S. Pat. No. 6,434,733, entitled, System and Method For High-Level Test Planning For Layout, discloses a prior solution to this problem. The '733 patent describes a method that includes partitioning a scan chain of a netlist into sets of orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are ordered based on the sets. According to one embodiment of the disclosed system and method, the scan-chain is partitioned into a number of different sets based on factors such as, the respective clock domains, edge sensitivity types, skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to place-and-route processes to be used as ordering limitations. Particularly, the ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set. The '733 patent specification asserts that by allowing ordering of scan cells within only respective sets, the system and method provides for placement and routing test mode logic that makes use of test mode information to thereby reduce the impact of test mode logic on mission mode circuit operation.
While earlier approaches to design of scan chains generally have been successful, there have been shortcoming with their use. For example, in complex IC designs such as system on a chip (SOC) designs, minimizing hold time violations for test mode logic and minimizing wire length and wire congestion are increasingly important issues. As explained above, one earlier solution to the problem of hold-time violations in scan chains has been to insert a delay element between sets of scan flip flops in different clock domains. However, the delay element itself takes up chip area and results in additional wires and increased overall scan chain wire length. Moreover, while limitations on scan ordering as suggested by the '733 patent can alleviate problems with placement-based scan chain ordering, there has existed a need for even more improvement in electronic design automation processes so as to further minimize hold-time violations and wire length and wire congestion for test mode logic. The present invention meets these needs.